This invention relates generally to integrated circuits and particularly to advanced integrated circuits which use lower supply voltages and smaller device geometries.
As integrated circuits scale to smaller and smaller geometries and supply voltages continue to decrease, a number of technologies which rely on voltage differences have become increasingly more difficult to implement in an effective fashion. The use of smaller voltages means that the speed at which devices operate may be diminished.
For example, pass transistors, sometimes also called transfer gates, interconnect basic building blocks of various components of integrated circuits. They can be used to connect a variety of different functional units, such as logic circuits. Pass transistors may be used, for example, in the following types of circuits: 1) microprocessors; 2) memories; 3) programmable logic; and 4) FPGAs. Among the myriad of applications for transfer gates are implementing a capacitive load adjustment capability such as that necessary with crystal oscillator circuits for frequency adjustment, implementing resistance adjustments such as those necessary for DC to DC converters, implementing programmable logic devices and implementing RF switching.
The ideal transfer gate can switch between the xe2x80x9conxe2x80x9d and xe2x80x9coffxe2x80x9d states without excessive power consumption. It primarily operates in the linear region to achieve low resistance. In addition, the parasitic capacitance associated with the transfer gate should be lower than that of the input or output capacitance of the circuits which it connects.
As integrated circuits have scaled to smaller and smaller geometries, designers have been effective in reducing the power supply voltages which such devices utilize. While it is very advantageous to decrease the necessary power supply voltage, a number of problems arise with respect to the xe2x80x9conxe2x80x9d resistance when the supply voltage decreases. See L. A. Glasser and D. W. Dobberpuhl, The Design and Analysis of VLSI Circuits, (December 1985) published by Addison-Wesley Publishing Co. at page 108. The transistor linear region resistance is inversely proportional to the gate to source voltage or xe2x80x9cVGSxe2x80x9d less the threshold voltage or xe2x80x9cVTxe2x80x9d.
As the supply voltage is scaled to ever lower voltages, this voltage difference can be reduced significantly. In addition, the transistor saturation voltage scales as (VGSxe2x88x92VT) decreases. As the device geometry scales, transistors may also run into what is known as xe2x80x9cvelocity saturationxe2x80x9d. Thus, the voltage range where the transistor operates in the linear region becomes increasingly narrow as geometries and supply voltages are scaled.
Conventionally, to reduce the xe2x80x9conxe2x80x9d resistance of a transfer gate, a designer may consider one of a couple of known approaches. The designer may increase the transistor width to thereby decrease the xe2x80x9conxe2x80x9d resistance. There is a linear relationship between increasing transistor width and decreasing xe2x80x9conxe2x80x9d resistance. However, the source/drain parasitic capacitance also increases linearly with increasing transistor width. Thus, the reduction of xe2x80x9conxe2x80x9d resistance in this fashion may result in an increase in parasitic capacitance which may be unacceptable. Particularly, since the resistance times the capacitance or xe2x80x9cRC productxe2x80x9d typically stays constant for a given technology, the increased width of the transfer gate does not significantly improve the performance of the transistor.
Another approach is to increase the transfer gate drive by using a floating gate transistor. See U.S. Pat. No. 5,457,653. However, the usefulness of this approach is limited by the data of retention requirement. That is, the floating gate voltage cannot exceed 4 to 5 megavolts per centimeter because the floating gate must retain its data for ten years and also for disturb concerns. This approach, therefore, implemented as an EEPROM, pays for increased gate drive with an increased potential for reliability problems and particularly the possibility of gate oxide breakdown and read disturb.
Because the transistor linear region resistance scales inversely with gate voltage less the threshold voltage, and the saturation voltage scales with gate voltage less the threshold voltage, if the gate voltage is equal to the supply voltage, the linear region xe2x80x9conxe2x80x9d resistance increases and the voltage range where the transistor operates in the linear region narrows. Surprisingly, this problem becomes more severe with the latest, scaled technologies. That is, as devices scale in terms of geometry and supply voltages, the problem is exacerbated for pass transistors. This means that, contrary to the well established industry conventional wisdom, at a certain point, continuing to scale devices and supply voltages may be counterproductive to improved pass transistor operating speed. Reducing supply voltage and scaling geometries, which have previously resulted in lower power consumption, could actually result in slower logic and pass transistors as supply voltages drop below 3 volts.
Thus, a solution to this trade off, which is more desirable than any currently envisioned, is needed to enable the continued increase in transfer gate speed with scaled technologies.
In accordance with one embodiment of the present invention, an integrated circuit device is formed on a semiconductor die adapted to operate with positive and negative supply voltages. The device includes a first group of integrated MOS transistors formed on the die. The first group of transistors have gate oxides. A second group of integrated MOS transistors are formed on the die which also have gate oxides. The gate oxides of the second group of transistors are thicker than the gate oxides of the first group of transistors. A path is provided to communicate boosted positive and negative supply voltages, greater than the positive and negative supply voltages, to at least some of the second group of transistors.
In accordance with another aspect, an integrated circuit device includes a first transistor having a gate electrode and a gate oxide. A second transistor has a gate electrode and a gate oxide. The gate oxide of the second transistor is thicker than the gate oxide of the first transistor. The second transistor gate electrode is selectively connectable to a positive or a negative bias voltage.
In accordance with yet another aspect, an integrated circuit device includes a first transistor having a gate electrode and a gate oxide. A second transistor has a gate electrode and a gate oxide, the gate oxide of the second transistor being thicker than the gate oxide of the first transistor. A source of a first and second positive potential is provided, the second positive potential being higher than the first positive potential. A source of negative potential is also provided. The gate electrode of the second transistor is selectively connectable to the higher positive potential or the negative potential. The source and drain of the second transistor is connected as a transfer gate to a pair of logic circuits so as to permit selective communication between the logic circuits through the second transistor.
In accordance with still another aspect, a transfer gate is implemented by a zero threshold transistor having a gate electrode. That gate electrode is selectively connectable to a negative potential.